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sanken electric co., ltd. introduction the lc5500 series is the power ic for the isolated type led driver which has an incorporated power mosfet, designed for input capacitorless applications, and making it possible for systems to comply with the harmonics standard (iec61000-3-2 class c). the controller adapts the average current control method for realizing high power factors, and the quasi-resonant topology contributes to high efficiency and low emi noise. the series is housed in either dip8 or to-220f-7l packages, depending on output power capability. the rich set of protection features helps to real- ize low component counts, and high performance-to-cost power supply. features and benefits ? dip8 package (lc551xd/lc552xd) and to-220f-7l package (lc552xf) ? integrated on-width control circuit (it realizes high power factor by average current control) ? integrated startup circuit (no external startup circuit necessary) ? integrated soft-start circuit (reduces power stress during start-up on the incorporated power mosfet and output rectifier) ? integrated bias assist circuit (improves the startup performance, suppresses v cc voltage droop during operation, allows reduction of vcc capacitor value as well as use of a ceramic capacitor) ? integrated leading edge blanking (leb) circuit ? integrated maximum on-width limit circuit lc5500 series single-stage power factor corrected off-line switching regulators figure 1. the lc5500 series packages for lower wattage versions are fully molded dip8s, with pin 7 removed for greater isolation. for higher wattages, the to-220f-7l fully molded package is provided, with three leadform options, all which provide a separation between pins 1 and 2. application information lc5500-an, rev.1.2 to-220f-7l (lf 3052) to-220f-7l (lf 3054) to-220f-7l (lf 3051) dip8 ? dual-chip structure, with an avalanche-guaranteed power mosfet (allows simplified surge suppressing circuits) ? protection features: ? overcurrent protection (ocp): pulse-by-pulse ? overvoltage protection (ovp): auto restart, ovp- activating pins vary by product series: ovp-activating pins series vcc isense ovp ocp lc551xd ? lc552xd ? lc552xf ? ? overload protection (olp): auto restart ? thermal shutdown (tsd): halts switching operation and latches in the off-state the product lineup for the lc5500 series provides the following options: part number mosfet v dss (min) (v) r ds(on) (max) ( ) isolation package p out * (w) 230 vac universal (wide) lc5511d 650 3.95 non- isolated dip8 13 10 lc5513d 1.9 20 16 lc5521d 3.95 isolated 13 10 lc5523d 1.9 20 16 LC5523F to-220f- 7l 60 40 lc5525f 1.1 80 55 *based on the thermal rating; the allowable maximum output power can be up to 120% to 140% of this value. however, maximum output power may be limited in an applications with low output voltage or short duty cycle. part number assignment lc55 nna abcd a product series name b indicates non-isolated or isolated: 1 ? non-isolated, 2 ? isolated c on-resistance of the incorporated mosfet: 1 ? 3.95 , 3 ? 1.9 , 5 ? 1.1 d indicates the package: d ? dip8, f ? to-220f-7l
2 sanken electric co., ltd. lc5500-an, rev.1.2 table of contents general specifications 1 block diagrams and pin descriptions 3 package drawings 5 electrical characteristics 9 application circuit examples 15 operation description 17 on-width control operation 17 startup operation 19 operation modes at startup 21 soft-start function 21 quasi-resonant operation and bottom-on timing 22 latch function 25 overvoltage protection (ovp) 26 overload protection (olp) 30 overcurrent protection (ocp) 32 input compensation function for overcurrent protection 33 ocp threshold voltage with and without the ocp input compensation circuit 33 thermal shutdown protection 35 maximum on-width limiting function 35 design considerations 35 peripheral components 35 transformer design 35 trace and component layout design 37
3 sanken electric co., ltd. lc5500-an, rev.1.2 s/gnd tsd leb d/st start up reg bias uvlo vcc ocp ovp osc ocp detection bottom reg control feedback olp drv comp isense q s r ota nf controller chip figure 2. lc551xd series functional block diagram (for non-isolated dip8 designs) lc551xd series terminal list table number name function 1 s/gnd mosfet source and gnd terminal for the controller chip 2 vcc supply voltage input and overvoltage protection (ovp) signal input 3 ocp overcurrent protection, quasi-resonant signal input terminal, and overvoltage protection (ovp) signal input 4 comp feedback phase-compensation input 5nf no function; must be externally connected to s/gnd pin with as short a trace as possible, for stable operation of the ic 6 isense output current sensing voltage input and overvoltage protection (ovp) signal input 7 ? pin removed 8 d/st mosfet drain terminal and input of the startup current block diagrams and pin descriptions this section provides block diagrams and pin descriptions of: ? lc551xd for non-isolated dip8 designs ? lc552xd for isolated dip8 designs ? lc552xf for isolated to-220-7l designs 1 2 3 4 8 6 5 d/st isense nf s/gnd vcc ocp comp pin-out diagram (lc551xd)
4 sanken electric co., ltd. lc5500-an, rev.1.2 s/gnd q s r tsd leb d/st fb startup reg bias uvlo vcc ocp ovp ovp osc ocp detection bottom reg control feedback olp drv nf controller chip figure 3. lc552xd series functional block diagram (for isolated dip8 designs) lc552xd series terminal list table number name function 1 s/gnd mosfet source and gnd terminal for the controller chip 2 vcc supply voltage input and overvoltage protection (ovp) signal input 3 ocp overcurrent protection, quasi-resonant signal input terminal, and overvoltage protection (ovp) signal input 4 fb feedback signal input and overload protection (olp) signal input 5nf no function; must be externally connected to s/gnd pin with as short a trace as possible, for stable operation of the ic 6 ovp overvoltage protection (ovp) signal input 7 ? pin removed 8 d/st mosfet drain terminal and input of the startup current 1 2 3 4 8 7 6 5 d/st ovp nf s/gnd vcc ocp fb pin-out diagram (lc552xd) s/gnd q s r tsd leb d/st fb startup reg bias uvlo vcc ocp ovp ovp osc ocp detection bottom reg control feedback olp drv controller chip figure 4. lc552xf series functional block diagram (for isolated to-220f-7l designs) lc552xf series terminal list table number name function 1 d/st mosfet drain terminal and input of the startup current 2 s/gnd mosfet source and gnd terminal for the controller chip 3 nc no connection 4 vcc supply voltage input and overvoltage protection (ovp) signal input 5 ocp overcurrent protection, quasi-resonant signal input terminal, and overvoltage protection (ovp) signal input 6 fb feedback signal input and overload protection (olp) signal input 7 ovp overvoltage protection (ovp) signal input 2 3 4 6 1 5 7 d/st s/gnd nc vcc ocp fb ovp 1 2 3 4 5 6 7 d/st s/gnd nc vcc ocp fb ovp 2 4 6 1 3 5 7 d/st s/gnd nc vcc ocp fb ovp pin-out diagrams (lc552xf) (lf 3051) (lf 3052) (lf 3054)
5 sanken electric co., ltd. lc5500-an, rev.1.2 package drawings this section provides dimensioned drawings of the dip8 and the to-220-7l packages. figure 5. dip8 package drawing 0 . 2 5 + 0 . 1 - 0 . 0 5 6.5 1 4 5 8 9.4 0.3 0.5 0.1 0.89 typ 4.2 0.3 3.3 3.4 0.1 0.2 (7.6 typ) 2.54 typ -0.05 -0.05 0.2 0.5 7.5 +0.3 +0.3 1.0 1.52 a lc b c a: part #: 55xx b: lot number 3 digits, plus d 1 st letter: last digit of year 2 nd letter: month jan to september: numeric october: o november: n december: d 3 rd letter: week date 1 to 10: 1 date 11 to 20: 2 date 21 to 31: 3 c: internal use control number leadframe material cu pin treatment: solder plating weight approximately 0.51g unit mm pb-free. device composition compliant with the rohs directive.
6 sanken electric co., ltd. lc5500-an, rev.1.2 b a lc 5.6 0.2 at base of pin at base of pin at tip of pin front view side view at tip of pin 0.3 5.850.15 5p1.170.15 50.5 0.2 1.1 0.2 7 6 5 4 3 2 1 10 15 0.5 10.4 7-0.55 +0.2 -0.1 7-0.62 0.15 2 0.15 2.8 +0.2 4.2 2.6 0.1 2.6 r-end 50.5 r-end -0.1 +0.2 0.45 2.540.6 5.080.6 0.5 0.5 0.5 0.5 gate burr unit: mm b: lot number 1 st letter: last digit of year 2 nd letter: month jan to september: numeric october: o november: n december: d 3 rd and 4 th letter: date 01 to 31: numeric 5 th letter: internal use control number package: to-220f-7l leadframe material: cu pin treatment: solder dip weight: approximately 1.45 g note: "gate burr" shows area where 0.3 mm (max) gate burr may be present. a: part # 55xxf ?3.2 0.2 figure 6. to-220f-7l (sanken leadform number 3051) package drawing leadform 3051 pin treatment pb-free. device composition compliant with the rohs directive.
7 sanken electric co., ltd. lc5500-an, rev.1.2 figure 7. to-220f-7l (sanken leadform number 3052) package drawing 5.6 0.2 0.3 5.850.15 5p1.170.15 50.5 0.2 1.1 0.2 7 6 5 4 3 2 1 10 15 0.5 10.4 7-0.55 +0.2 -0.1 7-0.62 0.15 2 0.15 2.8 +0.2 4.2 2.6 0.1 2.6 r-end front view side view -0.1 +0.2 0.45 5.080.6 0.5 0.5 0.5 0.5 b a gate burr lc at base of pin at base of pin at tip of pin unit: mm a: part # 55xxf b: lot number 1 st letter: last digit of year 2 nd letter: month jan to september: numeric october: o november: n december: d 3 rd and 4 th letter: date 01 to 31: numeric 5 th letter: internal use control number package: to-220f-7l leadframe material: cu pin treatment: solder dip weight: approximately 1.45 g ?3.2 0.2 note: "gate burr" shows area where 0.3 mm (max) gate burr may be present. leadform 3052 pin treatment pb-free. device composition compliant with the rohs directive.
8 sanken electric co., ltd. lc5500-an, rev.1.2 figure 8. to-220f-7l (sanken leadform number 3054) package drawing 0.5 0.5 0.5 0.5 7 6 5 4 3 2 1 7-0.62 7-0.55 0.2 10 (5.6) 0.2 2.8 0.3 15 0.15 2 b a gate burr -0.1 +0.2 0.5 3.8 3-( r1) 0.5 5 2.5 2.8 0.2 2.6 (1.1) 0.15 -0.1 +0.2 0.1 2.6 4.2 0.2 ?3.2 0.2 0.45 0.5 0.5 lc at base of pin 5p 1.17 0.15 = 5.85 0.15 plan view side view at base of pin at tip of pin at tip of pin unit: mm b: lot number 1 st letter: last digit of year 2 nd letter: month jan to september: numeric october: o november: n december: d 3 rd and 4 th letter: date 01 to 31: numeric 5 th letter: internal use control number package: to-220f-7l leadframe material: cu pin treatment: solder dip weight: approximately 1.45 g a: part # 55xxf note: "gate burr" shows area where 0.3 mm (max) gate burr may be present. leadform 3054 pin treatment pb-free. device composition compliant with the rohs directive.
9 sanken electric co., ltd. lc5500-an, rev.1.2 electrical characteristics this section provides separate sets of electrical characteristic data, using representative examples (refer to individual data- sheets for more details): ? lc551xd series (non-isolated): lc5513d is the example ? lc552xd series (isolated): lc5521d is the example ? lc552xf series (isolated): LC5523F is the example current direction is sink is positive (+) and source is nega- tive (?) in reference to the ic. lc5513d absolute maximum ratings t a = 25c, unless otherwise specified characteristic symbol notes pins rating unit drain current 1 i dpeak single pulse 8 ? 1 4.0 a single pulse avalanche energy 1 e as i lpeak = 2.7 a, v dd = 99 v, l = 20 mh 8 ? 1 86 mj supply voltage for controller chip v cc 2 ? 1 35 v ocp pin voltage v ocp 3 ? 1 ? 2.0 to 5.0 v comp pin voltage v comp 4 ? 1 ? 0.3 to 7.0 v isense pin voltage v isen 6 ? 1 ? 0.3 to 5.0 v allowable power dissipation of mosfet 2 p d1 8 ? 1 0.97 w operating ambient temperature t op D? 55 to 125 c storage temperature t stg D? 55 to 125 c channel temperature t ch D 150 c 1 refer to each individual product datasheet for details. 2 mounted on a 15 mm 15 mm pcb. lc5513d electrical characteristics (mosfet) t a = 25c, unless otherwise specified characteristic symbol test conditions pins min. typ. max. unit drain-to-source breakdown voltage 1 v dss 8 ? 1 650 DD v drain leakage current i dss 8 ? 1 DD 300 a on resistance 1 r ds(on) 8 ? 1 DD 1.9 switching time 1 t f 8 ? 1 DD 400 ns thermal resistance 1,2 r ch-c between channel and case DDD 35.5 c/w 1 refer to each individual product datasheet for details. 2 the thermal resistance between the channels of the mosfet and the case. t c measured at the center of the case top surface.
10 sanken electric co., ltd. lc5500-an, rev.1.2 lc5513d electrical characteristics (controller chip) t a = 25c, v cc = 20 v, unless otherwise specified characteristic symbol test conditions pins min. typ. max. unit startup operation operation start voltage v cc(on) 2 ? 1 13.8 15.1 17.3 v operation stop voltage* v cc(off) 2 ? 1 8.4 9.4 10.7 v operating current i cc(on) 2 ? 1 ? ? 3.7 ma startup circuit operation voltage v startup 8 ? 1 42 57 72 v startup current i cc(startup) v cc = 13 v 2 ? 1 ? 5.5 ? 3.0 ? 1.0 ma startup current threshold biasing voltage-1* v cc(bias)1 2 ? 1 9.5 11.0 12.5 v startup current threshold biasing voltage-2 v cc(bias)2 2 ? 1 14.4 16.6 18.8 v normal operation pwm operation frequency f osc 8 ? 1 11.0 14.0 18.0 khz maximum on-width t on(max) 8 ? 1 30.0 40.0 50.0 s comp pin control voltage lower limit v comp(min) 4 ? 1 0.55 0.90 1.25 v error amplifier reference voltage v sen(th) 6 ? 1 0.27 0.30 0.33 v error amplifier source current i sen(source) 4 ? 1 ? 11 ? 7 ? 3 a error amplifier sink current i sen(sink) 4 ? 1 3 7 11 a leading edge blanking time t on(leb) 3 ? 1 ? 500 ? ns quasi-resonant operation threshold voltage-1 v bd(th1) 3 ? 1 0.14 0.24 0.34 v quasi-resonant operation threshold voltage-2 v bd(th2) 3 ? 1 0.12 0.17 0.22 v protection operation ocp pin overcurrent protection (ocp) threshold voltage v ocp 3 ? 1 ? 0.54 ? 0.60 ? 0.66 v ocp pin source current i ocp 3 ? 1 ? 120 ? 40 ? 10 a ocp pin overvoltage protection (ovp) threshold voltage v bd(ovp) 3 ? 1 2.2 2.6 3.0 v overload protection (olp) threshold voltage-1 v comp(olp)1 4 ? 1 5.0 5.5 6.0 v overload protection (olp) threshold voltage-2 v comp(olp)2 4 ? 1 4.1 4.5 4.9 v isense pin ovp threshold voltage v isen(ovp) 6 ? 1 1.6 2.0 2.4 v vcc pin ovp threshold voltage v cc(ovp) 2 ? 1 28.5 31.5 34.0 v thermal shutdown activating temperature t j(tsd) ? 135 ? ? c *v cc(bias)1 > v cc(off) always.
11 sanken electric co., ltd. lc5500-an, rev.1.2 lc5521d absolute maximum ratings t a = 25c, unless otherwise specified characteristic symbol notes pins rating unit drain current 1 i dpeak single pulse 8 ? 1 2.5 a single pulse avalanche energy 1 e as i lpeak = 2.0 a, v dd = 99 v, l = 20 mh 8 ? 1 47 mj supply voltage for controller chip v cc 2 ? 1 35 v ocp pin voltage v ocp 3 ? 1 ? 2.0 to 5.0 v fb pin voltage v fb 4 ? 1 ? 0.3 to 7.0 v ovp pin voltage v ovp 6 ? 1 ? 0.3 to 5.0 v allowable power dissipation of mosfet 2 p d1 8 ? 1 0.97 w operating ambient temperature t op D? 55 to 125 c storage temperature t stg D? 55 to 125 c channel temperature t ch D 150 c 1 refer to each individual product datasheet for details. 2 mounted on a 15 mm 15 mm pcb. lc5521d electrical characteristics (mosfet) t a = 25c, unless otherwise specified characteristic symbol test conditions pins min. typ. max. unit drain-to-source breakdown voltage 1 v dss 8 ? 1 650 DD v drain leakage current i dss 8 ? 1 DD 300 a on resistance 1 r ds(on) 8 ? 1 DD 3.95 switching time 1 t f 8 ? 1 DD 250 ns thermal resistance 1,2 r ch-c between channel and case DDD 42 c/w 1 refer to each individual product datasheet for details. 2 the thermal resistance between the channels of the mosfet and the case. t c measured at the center of the case top surface.
12 sanken electric co., ltd. lc5500-an, rev.1.2 lc5521d electrical characteristics (controller chip) t a = 25c, v cc = 20 v, unless otherwise specified characteristic symbol test conditions pins min. typ. max. unit startup operation operation start voltage v cc(on) 2 ? 1 13.8 15.1 17.3 v operation stop voltage * v cc(off) 2 ? 1 8.4 9.4 10.7 v operating current i cc(on) 2 ? 1 ? ? 3.7 ma startup circuit operation voltage v startup 8 ? 1 42 57 72 v startup current i cc(startup) v cc = 13 v 2 ? 1 ? 5.5 ? 3.0 ? 1.0 ma startup current threshold biasing voltage-1 * v cc(bias)1 2 ? 1 9.5 11.0 12.5 v startup current threshold biasing voltage-2 v cc(bias)2 2 ? 1 14.4 16.6 18.8 v normal operation pwm operation frequency f osc 8 ? 1 11.0 14.0 18.0 khz maximum on-width t on(max) 8 ? 1 30.0 40.0 50.0 s fb pin voltage minimum limit v fb(min) 4 ? 1 0.55 0.90 1.25 v maximum feedback current i fb(max) 4 ? 1 ? 10 ? 25 ? 40 a leading edge blanking time t on(leb) 3 ? 1 ? 500 ? ns quasi-resonant operation threshold voltage-1 v bd(th1) 3 ? 1 0.14 0.24 0.34 v quasi-resonant operation threshold voltage-2 v bd(th2) 3 ? 1 0.12 0.17 0.22 v protection operation ocp pin overcurrent protection (ocp) threshold voltage v ocp 3 ? 1 ? 0.54 ? 0.60 ? 0.66 v ocp pin source current i ocp 3 ? 1 ? 120 ? 40 ? 10 a ocp pin overvoltage protection (ovp) threshold voltage v bd(ovp) 3 ? 1 2.2 2.6 3.0 v overload protection (olp) threshold voltage-1 v fb(olp)1 4 ? 1 5.0 5.5 6.0 v overload protection (olp) threshold voltage-2 v fb(olp)2 4 ? 1 4.1 4.5 4.9 v ovp pin ovp threshold voltage v ovp(ovp) 6 ? 1 1.6 2.0 2.4 v vcc pin ovp threshold voltage v cc(ovp) 2 ? 1 28.5 31.5 34.0 v thermal shutdown activating temperature t j(tsd) ? 135 ? ? c * v cc(bias)1 > v cc(off) always.
13 sanken electric co., ltd. lc5500-an, rev.1.2 LC5523F electrical characteristics (mosfet) t a = 25c, unless otherwise specified characteristic symbol test conditions pins min. typ. max. unit drain-to-source breakdown voltage 1 v dss 1 ? 2 650 DD v drain leakage current i dss 1 ? 2 DD 300 a on resistance 1 r ds(on) 1 ? 2 DD 1.9 switching time 1 t f 1 ? 2 DD 400 ns thermal resistance 1,2 r ch-f between channel and internal frame DDD 3.1 c/w 1 refer to each individual product datasheet for details. 2 the thermal resistance between the channels of the mosfet and the case. t c measured at the center of the case top surface. LC5523F absolute maximum ratings t a = 25c, unless otherwise specified characteristic symbol notes pins rating unit drain current* i dpeak single pulse 1 ? 2 9.2 a single pulse avalanche energy* e as i lpeak = 2.9 a, v dd = 99 v, l = 20 mh 1 ? 2 99 mj supply voltage for controller chip v cc 4 ? 2 35 v ocp pin voltage v ocp 5 ? 2 ? 2.0 to 5.0 v fb pin voltage v fb 6 ? 2 ? 0.3 to 7.0 v ovp pin voltage v ovp 7 ? 2 ? 0.3 to 5.0 v allowable power dissipation of mosfet* p d1 with infinite heatsink 1 ? 2 20.2 w without heatsink 1 ? 2 1.8 w internal frame temperature in operation t f D? 20 to 115 c operating ambient temperature t op D? 55 to 115 c storage temperature t stg D? 55 to 125 c channel temperature t ch D 150 c *refer to each individual product datasheet for details.
14 sanken electric co., ltd. lc5500-an, rev.1.2 LC5523F electrical characteristics (controller chip) t a = 25c, v cc = 20 v, unless otherwise specified characteristic symbol test conditions pins min. typ. max. unit startup operation operation start voltage v cc(on) 4 ? 2 13.8 15.1 17.3 v operation stop voltage* v cc(off) 4 ? 2 8.4 9.4 10.7 v operating current i cc(on) 4 ? 2 ? ? 3.7 ma startup circuit operation voltage v startup 1 ? 2 42 57 72 v startup current i cc(startup) v cc = 13 v 4 ? 2 ? 5.5 ? 3.0 ? 1.0 ma startup current threshold biasing voltage-1* v cc(bias)1 4 ? 2 9.5 11.0 12.5 v startup current threshold biasing voltage-2 v cc(bias)2 4 ? 2 14.4 16.6 18.8 v normal operation pwm operation frequency f osc 1 ? 2 11.0 14.0 18.0 khz maximum on-width t on(max) 1 ? 2 30.0 40.0 50.0 s fb pin voltage minimum limit v fb(min) 6 ? 2 0.55 0.90 1.25 v maximum feedback current i fb(max) 6 ? 2 ? 10 ? 25 ? 40 a leading edge blanking time t on(leb) 5 ? 2 ? 500 ? ns quasi-resonant operation threshold voltage-1 v bd(th1) 5 ? 2 0.14 0.24 0.34 v quasi-resonant operation threshold voltage-2 v bd(th2) 5 ? 2 0.12 0.17 0.22 v protection operation ocp pin overcurrent protection (ocp) threshold voltage v ocp 5 ? 2 ? 0.54 ? 0.60 ? 0.66 v ocp pin source current i ocp 5 ? 2 ? 120 ? 40 ? 10 a ocp pin overvoltage protection (ovp) threshold voltage v bd(ovp) 5 ? 2 2.2 2.6 3.0 v overload protection (olp) threshold voltage-1 v fb(olp)1 6 ? 2 5.0 5.5 6.0 v overload protection (olp) threshold voltage-2 v fb(olp)2 6 ? 2 4.1 4.5 4.9 v ovp pin ovp threshold voltage v ovp(ovp) 7 ? 2 1.6 2.0 2.4 v vcc pin ovp threshold voltage v cc(ovp) 4 ? 2 28.5 31.5 34.0 v thermal shutdown activating temperature t j(tsd) ? 135 ? ? c *v cc(bias)1 > v cc(off) always.
15 sanken electric co., ltd. lc5500-an, rev.1.2 application circuit examples this section provides typical application circuits, using represen- tative examples (refer to individual datasheets for more details): ? lc551xd series (non-isolated) ? lc552xd series (isolated) ? lc552xf series (isolated) 5 1 2 3 d/st 8 s/gnd vcc controller chip c2 c5 d8 u1 d1 d3 d2 d4 f1 l1 c1 d5 c4 dz1 comp d6 t1 c3 d7 l2 led ocp isense nc r1 c6 d9 s/gnd (rocp) r2 r3 r4 r5 r 6 r7 vac c8 c7 c9 c11 c12 lc551x d 4 6 c10 r8 c2 c6 c5 d8 + - pc1 u2 dz1 d1 d3 d2 d4 f1 l1 c1 q1 d5 c4 c3 t1 d6 d7 dz2 pc2 l2 led r1 pc2 d9 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 ( rocp) r2 r3 r4 r5 r6 vac pc1 r7 c7 c8 c10 c9 c11 c12 c13 c14 c15 c16 c17 5 1 2 3 d/st 8 s/gnd vcc controller chip u1 ovp ocp fb nc s/gnd lc552xd 6 4 figure 9. non-isolated application circuit example, with lc551xd series device figure 10. isolated application circuit example, with lc552xd series device
16 sanken electric co., ltd. lc5500-an, rev.1.2 figure 11. isolated application circuit example, with lc552xf series device t1 c2 d1 d3 d2 d4 f1 l1 c1 d5 l2 d6 d9 d8 + - pc1 u2 dz1 q1 dz2 led pc2 c4 pc2 d7 r1 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 7 ovp r4 r5 r6 va c pc1 r7 c7 c8 c10 c11 c12 c13 c14 c15 c16 c9 c17 vcc 6 ocp fb c6 5 4 vcc 3 nc s/gnd 2 r20 1 d/st u1 c5 c3 (rocp) r2 r3 lc552xf controller chip
17 sanken electric co., ltd. lc5500-an, rev.1.2 operation description all of the parameter values used in these descriptions are typi- cal values, unless they are specified as minimum or maximum. this section describes ic operations as it is used for led lighting power supply applications. about current direction, "+" indicates sink current toward the ic and "?" indicates source current from the ic. the pin numbers parenthesized represent lc552xf num- bers. on-width control operation lc551xd series (non-isolated designs) figure 12 shows the peripheral circuit at the comp pin of the lc551xd, and figure 13 shows the on-width control. the output control is done by voltage mode control, which controls on-width depending on output load, and average current control. as showed in figure 13, in the average current control operation, the output current detection resistor voltage is compared against the reference voltage by the ota circuit, and its output is aver- aged at comp pin. this voltage is compared against the internal oscillator (osc) by the fb comparator in order to control the on-width for the average current control operation. here, osc indicates the oscillator circuit, which controls the pwm operation frequency, quasi-resonant oscillation, and the maximum on-width limit. for the lc551xd devices, the recommended value of c6, which is connected to the comp terminal, is approximately 2.2 f. the constant output current control of the output is done as below: ? when the output load current becomes less than the target value, the isense pin voltage becomes low. this causes the averaged ota circuit output voltage at the comp pin to become high, which increases the on-width and the output current. ? when the output current becomes greater than the target value, the circuits operate in the opposite way. the averaged voltage at the comp pin becomes low, and reductions result in the on-width and the output current. figure 14 shows the average input current waveform. the aver- aged comp pin voltage becomes constant, and the duty cycle control becomes based on the e in voltage (c2 voltage in figure 9). it makes an averaged input current sine waveform which realizes a high power factor. lc552xd and lc552xf series (isolated designs) figure 15 shows the peripheral circuit at the fb pin of the lc552xd/ lc552xf, and figure 16 shows the on-width control. the output figure 13. on-width control, lc551xd series 1 ? + ? + 4 6 fb ota led current lc551xd detection resistor isense s/gnd comp comp pin voltage gate on-width gate on-width drain current osc v comp osc 3 1 comp r ocp c6 s/gnd ise nse d7 ocp lc551xd r3 6 4 figure 12. comp pin peripheral circuit
18 sanken electric co., ltd. lc5500-an, rev.1.2 figure 14. averaged input current waveform, lc551xd series comp pin voltage s/gnd e in drain current averaged input current 1(2) ? + ? + 4(6) led current detection resistor s/gnd fb c6 r7 fb pin voltage gate on-time gate on-time drain current osc v fb osc pc (lc552xf) lc552xd control is done by voltage mode control, which controls on-width depending on output load, and average current control. as showed in figure 16, in the average current control operation, the output current detection resistor voltage is compared by the operational amplifier, and its output is sent to the fb pin in con- junction with the opto-coupler and averaged at the fb pin. the fb pin voltage is compared against the internal oscillator (osc) by the fb comparator in order to control the on-width for aver- aged current control operation. here, osc indicates the oscillator circuit, which controls the pwm operation frequency, quasi- resonant oscillation, and the maximum on-width limit. for the lc552xd and lc552xf series devices, the recommended value of c6, which is connected to the fb pin, is approximately 2.2 f. the constant output current control of the output is done as below. ? when the output load current becomes less than the target value, the secondary current detection resistor voltage becomes low and it results in low feedback current from the opto-coupler. it causes the averaged voltage at the fb pin to become high, and results in increases of the on-width and the output current. ? when the output current becomes more than the target value, the circuits operate in the opposite way the averaged voltage at the fb pin becomes low, which reduces the on-width and the output current. figure 17 shows the average input current waveform. the aver- aged fb pin voltage becomes constant, and the duty cycle control becomes based on the e in voltage (c2 voltage in figures 10 and 11). it makes an averaged input current sine waveform which realizes a high power factor. figure 15. fb pin peripheral circuit 3(5) 1(2) r ocp s/gnd 4(6) d7 fb c6 pc1 ocp r3 r7 lc552xd (lc552xf) figure 16. on-width control, lc552xd and lc552xf series
19 sanken electric co., ltd. lc5500-an, rev.1.2 figure 17. averaged input current waveform, lc552xd and lc552xf series fb pin voltage s/gnd e in drain current averaged input current d/st vcc s/gnd d v p c2 2(4) 8(1) c4 1(2) d l2 lc55xxd (lc552xf) d5 r1 vcc pin voltage = 3.7ma i cc(on) (max) sto p startup i cc 9.4 v v cc(off) v cc(on) 15.1 v figure 18. vcc pin peripheral circuit figure 19. v cc versus operation current, i cc startup operation figure 18 shows the vcc pin peripheral circuit. the integrated startup circuit is connected to the d/st pin, and it generates a constant current, i cc(startup) = ?3.0 ma, to charge capacitor c4 at the vcc pin. during this process, when vcc voltage reaches v cc(on) = 15.1 v, the ic starts operation, and when its voltage exceeds v cc(bias)2 = 16.6 v, the startup circuit stops, in order to eliminate its own power consumption. the startup time is determined by the c4 capacitance and is expressed by the formula below: t start c 4 |i cc(startup) | v cc(on) ? v cc(init) (1) where t start is the startup time (s), and v cc(init) is the vcc pin initial voltage (v). a ceramic or film capacitor can be used for c4, and a value of 0.22 to 22 f is generally recommended. figure 19 shows the relationship between vcc voltage and the operating current, i cc . when vcc voltage reaches v cc(on) = 15.1 v, the controller circuit operation begins and the operating current increases. after that, if vcc voltage decreases to v cc(off) = 9.4 v, the undervoltage lockout (uvlo) circuit stops control- ler circuit operation, and the operation state returns to the startup phase. after the control circuit starts up, the auxiliary winding (d in figure 18) voltage, rectified by diode d5, powers the vcc pin. vcc voltage must satisfy these conditions: v cc(bias)1 (max) = 12.5 v < v cc < v cc(ovp) (min) = 28.5 v initially, target 20 v in a transformer design, and then optimize its winding turns in a way that vcc voltage stays within that speci- fied range over the conceivable input voltage range and output load conditions.
20 sanken electric co., ltd. lc5500-an, rev.1.2 figure 20 shows the vcc voltage behavior at the startup phase. immediately after the controller circuit starts operation, the aux- iliary winding voltage, v d , has not yet reached its design target value, which is determined by the transformer auxiliary winding turns. therefore, as shown figure 20, vcc voltage starts decreas- ing after the startup circuit turns off at v cc(bias)2 = 16.6 v. after a while, if the vcc voltage reaches the startup current threshold biasing voltage-1, v cc(bias)1 = 11.0 v, the bias assisting function is activated in order to avoid further voltage drop and vcc voltage becomes nearly constant. thanks to this function, the c4 value can be small, which results in shortening the startup period and improv- ing the response time of the vcc pin overvoltage protection. figure 21 shows the positive dependency of vcc voltage on output current. this is caused by the surge voltage, which occurs on the d/st pin at the turn-off edge of the incorporated power mosfet. the surge voltage is coupled to the auxiliary winding and it charges-up c4 more than the design target. in order to avoid this, insert r1 in series with d5 as shown in figure 22, and choose a value for it between several ohms to several tenths of ohms. in addition, the transformer winding structure has influence on v cc fluctuation and the two items below are examples of worsen- ing it: ? poor coupling between the primary and secondary windings (this causes high surge voltage and is seen in a design with low output voltage and high output current). ? poor coupling between the secondary winding and the auxiliary winding d (this increases the effect of the surge voltage on the auxiliary winding voltage). against those items, the two items below are commonly used as techniques for improvement (its construction with triple insulation wires as primary winding and/or secondary winding, and without margin region): ? separate the auxiliary winding d from the primary windings p1 and p2 (figure 23(a)); p1 and p2 are two separated primary windings. ? place the auxiliary winding d within the secondary winding s1 in order to improve the coupling of those windings (figure 23(b)); s1 is the secondary output winding. i out vcc pin voltage with r1 without r1 d v cc d5 c4 2(4) 1(2) lc55xxd (lc55xxf) s/gnd r1 added figure 21. v cc versus i out with and without resistor r1 figure 22. vcc pin peripheral circuit with r1 figure 20. v cc at startup period time = 15.1 v = 11.0 v vcc pin voltage v cc(off) v cc(on) = 16.6 v v cc(bias)2 v cc(bias)1 = 9.4 v operation start startup successful startup circuit off bias assisting startup failure figure 23. transformer winding structures: (a) auxiliary winding apart from the primary windings, and (b) auxiliary winding within secondary winding p2 d p1 s1 s1 p1 s1 d p2 s1 p1, p2: primary winding s1: secondary winding d: auxiliary winding core bobbin p1, p2: primary winding s1: secondary winding d: auxiliary winding core bobbin (a) (b)
21 sanken electric co., ltd. lc5500-an, rev.1.2 operation modes at startup figure 24 shows the operation modes during the startup phase of the lc551xd, and figure 25 shows those for the lc552xd and lc552xf. note that ocp pin voltage, which determines the tim- ing of quasi-resonant operation, is in positive voltage on the ocp pin, in reference to the s/gnd pin. during two periods below at startup, ic operation is set to pwm, with f osc = 14 khz: ? while the comp pin voltage (for lc551xd) and fb pin volt- age (for lc552xd and lc552xf), in reference to s/gnd, are 0 to 0.9 v (the control voltage lower limit for the comp pin, v comp(min) , and fb pin, v fb(min) ): during this period, on-width is fixed at the leading edge blanking time, t bw = 500 ns. ? until the quasi-resonant signal (ocp pin voltage) reaches the quasi-resonant operation threshold voltage-1, v bd(th1) = 0.24 v: during this period, the output voltage is low; therefore, the auxiliary winding voltage, v d , is low. thus the quasi-reso- nant signal is low. after those startup operations the output voltage starts increasing, when the ocp pin voltage reaches v bd(th1) = 0.24 v, the ic is switched to quasi-resonant operation (figure 26). soft-start function the soft-start function reduces power stress on the incorporated mosfet and secondary rectifier during the startup phase. lc551xd series (non-isolated designs) the soft-start operation begins when the comp pin voltage reaches v comp(min) = 0.9 v and lasts until the output current becomes constant. during that period, the output power gradually increases. during this period, check the items below: ? vcc pin voltage does not drop to the operation stop voltage, v cc(off) ? output current reaches the target value before the overload pro- tection (olp) is activated by the comp pin voltage reaching v comp(olp)2 = 4.5 v v cc pin voltage comp pin voltage output (led) current, i out drain current, i d s/gnd ic turn on s/gnd gnd(i out ) duration pwm (qr) v comp(min) = 0.90 v v cc (bias 1 ) = 11.0 v soft-start period target current gnd( i d ) constant current operation t on = t bw (500 ns) vcc pin voltage fb pin voltage output (led) current, i out drain current, i d s/gnd ic turn on s/gnd gnd(i out ) duration pwm (qr) v fb (min) = 0.90 v v cc (bias 1 ) = 11.0 v soft-start period target current gnd( i d ) constant current operation t on = t bw (500 ns) figure 24. soft-start operation waveforms at startup (lc551xd) figure 25. soft-start operation waveforms at startup (lc552xd/ lc 552xf) gnd(i d ) s/gnd v bd(th1) pwm operation quasi-resonant operation (qr) ocp pin voltage drain current, i d figure 26. ocp pin voltage (with time scale expanded)
22 sanken electric co., ltd. lc5500-an, rev.1.2 lc552xd/lc552xf series (isolated designs) the soft-start oper- ation begins when the fb pin voltage reaches v fb(min) = 0.9 v and lasts until the output current becomes constant. during that period, the output power gradually increases. during this period, check the items below: ? vcc pin voltage does not drop to the operation stop voltage, v cc(off) ? output current reaches the target value before the overload protection (olp) is activated by the fb pin voltage reaching v fb(olp)2 = 4.5 v quasi-resonant operation and bottom-on timing figure 27 shows a basic circuit diagram of a flyback converter, in which the energy of the transformer is transferred to the second- ary side after the primary side mosfet turns off. when the primary side mosfet keeps turning off after the energy is transferred to the secondary, the mosfet drain node begins free oscillation based on the transformer l p , and c v across the drain and source pins, after the energy is completely trans- ferred to the secondary. the quasi-resonant operation is the v ds bottom-on operation that turns on the mosfet at the bottom point of v ds free oscillation. because of that, switching loss and switching noise are reduced. therefore, highly efficient and low noise converters can be realized. figure 28 shows an ideal v ds waveform of this mode. turning on the mosfet at the bottom of v ds is done by creating certain duration, delay time t ondly , as figure 28 shows from the start of v ds free oscillation. this delay time is created by exploiting the auxiliary winding voltage, which synchronizes to the drain voltage v ds waveform and it is called the quasi-resonant signal. figure 27. basic flyback converter circuit e in i off v out i d e f n p p n s c v l c out e in : input voltage e f : flyback voltage e f ( v out + v f ) = n p n s (2) n p : number of turns in the primary winding n s : number of turns in the secondary winding v out : output voltage v f : forward voltage of the secondary rectifier i d : drain current of the power mosfet i off : current running through the secondary rectifier during the power mosfet off-period c v : voltage resonant capacitor l p : primary inductance figure 28. waveforms of the ideal bottom-on mode e in ondly t bottom point e f i off d i t on v ds half cycle of free oscillation, t ondly l p c v
23 sanken electric co., ltd. lc5500-an, rev.1.2 figure 29 shows the ocp pin peripheral circuit. d6, r4, c7 and d7 form a delay circuit, and the auxiliary winding flyback volt- age, e rev1 , is fed through the delay circuit and provides positive voltage, the quasi-resonant signal, to the ocp pin. figure 30 shows the forward voltages versus the power supply. after the power mosfet turns off, the quasi-resonant signal immediately goes up and it exceeds the quasi-resonant opera- tion threshold voltage-1, v bd(th1) = 0.24 v. after this occurs, the power mosfet remains off until the quasi-resonant sig- nal comes down enough to cross the quasi-resonant opera- tion threshold voltage-2, v bd(th2) = 0.17 v. then the power mosfet again turns on. in addition, at the point, the threshold voltage goes up to v bd(th1) automatically to prevent malfunction of the quasi-resonant operation from noise interference.. during that period, c7 must cause a delay time, t ondly , such that the power mosfet turns on at the bottom point of v ds ; so select an appropriate c7 value. r3 is recommended to be between 100 and 330 , and c5 to be between 100 and 470 pf. r4 must set the range for the quasi-resonant signal: greater than or equal to v bd(th1) under input and output conditions where v cc becomes lowest, but less than the ocp pin overvoltage protec- tion (ovp) threshold voltage, v ocp(ovp) = 2.6 v, under condi- tions where v cc becomes highest. figure 31 defines the pulse width of the quasi-resonant signal. for initiating quasi-resonant operation, the quasi-resonant signal pulse width between the two points v bd(th1) and v bd(th2) , t qr , must be equal to 1.2 s or more. this pulse width must be ensured, while at the same time the ocp pin peak voltage, v bd(pk) , is recommended to be between 1.5 and 2.0 v. both conditions should be satisfied throughout the power supply input and output ranges, over varia- tions in r3 and r4 actual component values. figure 29. ocp pin peripheral circuit figure 30. auxiliary winding voltage and quasi-resonant signal pulse width, t qr 1.2 s s/gnd v bd(pk) , 1.5 to 2.0 v recommended, but less than 2.6 v v bd(th1) = 0.34 v (max) v bd(th2 ) = 0.22 v (max) figure 31. definition of the pulse width of the quasi-resonant signal 8(1) s/gnd v cc d/st ocp 3(5) 2(4) c2 d5 r1 c4 t1 d p r ocp c3 r4 d6 c7 e in e f e in flyback voltage forward voltage clamping snubber 1(2) c5 r3 d7 lc5500 v bd e rev 1 e fw 1 0 e fw 1 e rev1 t on d v bd(th1) v bd(th2) 0 quasi - resonant signal v bd auxiliary winding voltage v
24 sanken electric co., ltd. lc5500-an, rev.1.2 the formula below is used to calculate r4: r 4 = r 3 ( v cc ? v bd(pk) ? 2 v f ) v bd(pk) (3) given r3 = 220 , v bd(pk) = 1.5 v, v cc = 16 v, and the v f of d6 and d7 = 0.8 v. r4 is approximately 1.89 k , and it is 1.8 k in the e12 series. if the pulse width is not satisfied, increase r3 or decrease r4, in order to raise v bd(pk) . alternatively, increasing the capacitance of resonant capacitor c3 is also effective because it widens the free oscillation period. however, it causes an additional switching loss increase; therefore, ensure the ic temperature rise is acceptable. figure 32 shows two different ocp pin waveforms, comparing transformer coupling conditions between the primary and second- ary winding. the poor coupling tends to happen in a low output voltage (small number of leds) transformer design with high n p / n s turns ratio (n p and n s indicate the number of turns of the primary winding and secondary winding, respectively), and it results in high leakage inductance. the poor coupling causes high surge voltage ringing at the power mosfet drain pin when it turns off. that high surge voltage ringing is coupled to the auxil- iary winding and then the inappropriate quasi-resonant signal, as in figure 32b, is created. the ocp pin has a blanking period of 250 ns (max) to avoid reacting to it, but if the surge voltage con- tinues longer than that period, the ic responds to it and repeat- edly turns the power mosfet on and off at high frequency. this results in an increase of the mosfet power dissipation and temperature, and it can be damaged. if this phenomenon is observed, countermeasures include: ? place c5 as close to the ocp and s/gnd pins as possible ? separate the loop trace between the ocp pin and the s/gnd pin from any high current trace ? loosen the transformer coupling between the auxiliary winding and primary winding ? reinforce the clamping snubber circuit to reduce the surge voltage in addition, the ocp pin waveform during operation should be measured by connecting test probes with leads to the ocp pin and the gnd pin as short as possible, in order to measure any surge voltage correctly. timing adjustment of the bottom-on is done by selecting the value of c7 (figure 29). to do so, observe the power mosfet drain voltage, v ds , the drain current, i d , and the quasi-resonant signal. then optimize the c7 value to adjust the delay time of t ondly so that the mosfet turns on at the bottom point of v ds . figure 32. ocp pin waveform of a poorly coupled transformer (b) (a) proper ocp voltage, e rev2 = 2.6 v v ocp(ovp) v bd(th1) = 0.24 v v bd(th2) = 0.17 v s/gnd ocp pin blanking time, 250 ns (max) (b) inappropriate ocp voltage, e rev2
25 sanken electric co., ltd. lc5500-an, rev.1.2 as shown in figure 33: ? if the turn-on point is earlier than the bottom of the v ds signal, it causes higher switching losses. in that situation, delay the turn-on point by increasing the c7 value. ? in the converse situation, if the turn-on point is later than the v ds bottom point, it also causes higher switching losses, but in that case, advance the turn-on point by decreasing the c7 value. latch function thermal shutdown (tsd) protection is latched. when the latch circuit is activated, the ic stops switching operation, and there- fore the vcc voltage declines. however, the startup circuit turns on again when v cc reaches v cc(bias)1 = 11.0 v, in order to avoid reaching the operation stop- figure 33. effects of failure to turn on precisely at the v ds bottom point: (left) turn-on too early, (right) turn-on too late i off v ds t on i d s/gnd v ocp s/gnd t on auxiliary winding voltage i off v ds i d v ocp auxiliary winding voltage s/gnd v bd(th2) v bd(th1) s/gnd v bd(th2) v bd(th1) v ds v ds (p eak) 2 ac mains frequency ac mains frequency (50 hz / 60 hz) early turn-on point delayed turn-on point e in (max) gnd f r 2 l p c v 1 bottom point free oscillation, f r bottom point free oscillation, f r turn-on occurring after the v ds bottom point turn-on occurring before the v ds bottom point
26 sanken electric co., ltd. lc5500-an, rev.1.2 ping voltage, v cc(off) = 9.4 v. thus ic operation in latch mode is maintained. to release the ic from latch mode, cut off the ac mains and let vcc voltage drop below v cc(off) . overvoltage protection (ovp) lc551xd series (non-isolated designs) the lc551xd series has three ovp activation methods link to the vcc pin, to the ocp pin, and to the isense pin: ? vcc pin overvoltage protection. figure 34 shows the wave- forms of the ovp function on the vcc pin. when the vcc pin voltage with reference to the s/gnd pin reaches and exceeds v cc(ovp) = 31.5 v, ovp is activated and the ic stops switching operation. during this function, the bias assist function is dis- abled, and the vcc voltage decreases to v cc(off) = 9.4 v. after that, the startup circuit is activated, and the operation begins intermittent operation by repeating the restart and operation pro- cess as long as the ovp condition remains. in addition, because vcc voltage is proportional to the output voltage, it can be used to detect an output overvoltage event, such as open load condition. in this situation, the detecting voltage is expressed by the formula below: = v out(ovp) 31.5 (v) v cc (normal operation) v out (normal operation) (4) figure 34. waveforms when vcc pin ovp is being activated (lc551xd) comp pin voltage drain current, i d vcc pin voltage
27 sanken electric co., ltd. lc5500-an, rev.1.2 ? ocp pin overvoltage protection. figure 35 shows the ocp pin ovp function. when the ocp pin voltage with reference to the s/gnd pin reaches v ocp(ovp) = 2.6 v or more, ovp is activated. during this function, the bias assist function is disabled, and thus the ic enters intermittent operation as described in the vcc pin ovp section, above. this can be used as protection in the event that the quasi-resonant signal setup is mistaken or excess load current happens in the use of a poor coupling transformer between the primary and secondary winding. ? isense pin overvoltage protection. figure 36 shows the isense pin ovp operation. when the isense pin voltage with reference to the s/gnd pin reaches and exceeds v isen(ovp) = 2.0 v or more, ovp is activated. during this function, the bias assist function is disabled, and thus the ic enters intermittent operation as described in the vcc pin ovp section, above. as shown in figure 9, with zener diode dz1 this function can be used to detect an excess output voltage, such as caused by an open load condition, and protect the circuit. figure 36. waveforms when isense pin ovp is being activated (lc551xd) drain current, i d vcc pin voltage v bd(ovp) = 2.6v v cc(on) = 15.1v v cc(off) = 9.4v ocp pin voltage comp pin voltage vcc pin voltage v cc(on) = 15.1v v cc(off) = 9.4v drain current, i d v comp(min) = 0.90v isense pin voltage v isen(ovp) = 2.0v t on = t on(leb) (500ns) figure 35. waveforms when ocp pin ovp is being activated (lc551xd)
28 sanken electric co., ltd. lc5500-an, rev.1.2 lc552xd/lc552xf series (isolated designs) the lc552xd and lc552xf series have three ovp activation methods link to the vcc pin, to the ocp pin, and to the ovp pin: ? vcc pin overvoltage protection. figure 37 shows the wave- forms of the ovp function. when the vcc pin voltage with ref- erence to the s/gnd pin reaches and exceeds v cc(ovp) = 31.5 v or more, ovp is activated and the ic stops switching operation. during this function, the the bias assist function is disabled, and the vcc voltage decreases to v cc(off) = 9.4 v. after that, the startup circuit is activated, and the operation begins intermittent operation by repeating the restart and operation process as long as the ovp condition remains. in addition, because vcc voltage is proportional to the output voltage, it can be used to detect output overvoltage events, such as open load condition. in this situation, the detecting voltage is expressed by equation 4. figure 37. waveforms when vcc pin ovp is being activated (lc552xd and lc552xf) fb pin voltage vcc pin voltage v cc(ovp) = 31.5v v cc(on) = 15.1v v cc(off) = 9.4v drain current, i d v fb(min) = 0.90v t on = t on(leb) (500ns)
29 sanken electric co., ltd. lc5500-an, rev.1.2 figure 39. waveforms when ovp pin ovp is being activated (lc552xd and lc552xf) drain current, i d vcc pin voltage v ocp(ovp) = 2.6v v cc(on) = 15.1v v cc(off) = 9.4v ocp pin voltage figure 38. waveforms when ocp pin ovp is being activated (lc552xd and lc552xf) fb pin voltage vcc pin voltage v cc(on) = 15.1v v cc(off) = 9.4v drain current, i d v fb(min) = 0.90v ovp pin voltage v ovp(ovp) = 2.0v t on = t on(leb) (500ns) ? ocp pin overvoltage protection. figure 38 shows the ocp pin ovp function. when the ocp pin voltage with reference to the s/gnd pin reaches v ocp(ovp) = 2.6 v, ovp is activated. during this function, the bias assist function is disabled, and thus the ic enters intermittent operation as described in the vcc pin ovp section, above. this can be used as protection in the event the quasi-resonant signal setup is mistaken or excess load current happens in the use of a poor coupling transformer between the primary and secondary winding. ? ovp pin overvoltage protection. figure 39 shows the ovp pin ovp function. when the ovp pin voltage with reference to the s/gnd pin reaches and exceeds v ovp(ovp) = 2.0 v, ovp is activated. during this function, the bias assist function is disabled, and thus the ic enters intermittent operation as described in the vcc pin ovp section, above.. as shown in figure 10 and figure 11, with pc2 this function can be used to detect high output voltage, such as an open load condition.
30 sanken electric co., ltd. lc5500-an, rev.1.2 overload protection (olp) if the mosfet drain current is limited by the overcurrent pro- tection for a certain delay period, t dly , overload protection is activated and the ic enters intermittent oscillation mode opera- tion. this reduces the power-up stress on the incorporated power mosfet and secondary rectifier. lc551xd series (non-isolated designs) figure 40 shows the peripheral circuit at the comp pin, and figure 41 shows opera- tion when olp is activated. at an overload condition, the output voltage, the vcc pin volt- age, and the isense pin voltage drop. when the vcc pin volt- age reaches v cc(bias) = 11.0 v, the bias assist function is enabled in order to avoid reaching v cc(off) = 9.4 v. when the isense pin voltage reaches v sen(th) = 0.30 v, the output of the ota circuit becomes zero, and therefore the internal constant current source at the comp pin starts charging capacitor c6. when the comp pin voltage reaches overload protection threshold voltage-2, v comp(olp)2 = 4.5 v, the on-width is set to the leading edge blanking time, t on(leb) = 500 ns. meanwhile, the capacitor charging is ongoing and when it reaches overload protection threshold voltage-1, v comp(olp)1 = 5.5 v, the switch- ing operation stops. at the same time, the startup circuit is acti- vated and the operation begins intermittent operation by repeating the restart and operation stop processes as long as the overload condition remains. figure 40. comp pin peripheral circuit figure 41. waveforms when olp is being activated (lc551xd) v comp(olp)2 = 4.5v v comp(olp)1 = 5.5v comp pin voltage vcc pin voltage v cc(on) = 15.1v drain current, i d t on = t on(leb) (500ns) v cc(bias)1 = 11.0v v cc(off) = 9.4v v comp(min) = 0.90v
31 sanken electric co., ltd. lc5500-an, rev.1.2 lc552xd/lc552xf series (isolated designs) figure 42 shows the peripheral circuits at the fb pin of the lc552xd/lc552xf series and figure 43 shows the waveforms when the overload protection (olp) is activated. at an overload condition, the output voltage drops and it results in a feedback signal from the secondary output becoming zero. after that, the internal constant current source at the fb pin starts to charge the c6 capacitor. when the fb pin voltage reaches the overload protection threshold voltage-2, v fb(olp)2 = 4.5 v, the on-width is set to leading edge blanking time, t on(leb) = 500 ns. in the mean- while, the capacitor charging is ongoing and when it reaches at overload protection threshold voltage-1, v fb(olp)1 = 5.5 v, the switching operation stops. at the same time, the startup circuit is activated and the operation begins intermittent operation by repeating the restart and operation stop processes as long as the overload condition remains. figure 42. fb pin peripheral circuit figure 43. waveforms when olp is being activated (lc552xd/ lc552xf) v fb(olp)2 = 4.5v v fb(olp)1 = 5.5v fb pin voltage vcc pin voltage v cc(on) = 15.1v drain current, i d t on = t on(leb) (500ns) v cc(bias)1 = 11.0v v cc(off) = 9.4v v fb(min) = 0.90v 7vreg r ocp s/gnd ocp 1(2) 4(6) fb c6 lc552x d r7 (lc552x f) 3(5)
32 sanken electric co., ltd. lc5500-an, rev.1.2 overcurrent protection (ocp) the overcurrent protection (ocp) feature monitors the power mosfet drain current on a pulse-by-pulse basis, in order to limit output power. the drain current is detected by a current detection resistor, r ocp , and the voltage across it, v rocp , is fed through r3 to the ocp pin to be detected by it. when the r ocp voltage, v rocp , reaches the value of the following formulas, the power mosfet turns off. =? v rocp |v ocp | + r 3 |i ocp | (5) where v ocp : overcurrent detection threshold voltage, -0.60 v, and i ocp : ocp pin source current, -40 a. in order to minimize effects of variation in the internal resis- tor, r3 (figure 44) is recommended to have a value from 100 to 330 . and c5 is recommended to have a value from 100 to 470 pf, with good temperature characteristics. selecting larger capacitances slows ocp response, and results in an increase in the drain current peak at transient conditions, such as start-up. because the ocp function is designed for peak current detection, there is a chance that it will react to the surge current at the power mosfet turn-on edge. in order to avoid this, the leading edge blanking time is set. the leading edge blanking time, t on(leb) = 500 ns, is set. the surge current pulse width must be less than t on(leb) as shown in figure 45. in case its width is longer than that, try these mea- sures: ? adjust the turn-on point to the v ds bottom point ? reduce the voltage resonant capacitor c v (c3 in figure 44) capacitance ? reduce the secondary rectifier snubber capacitor capacitance with the quasi-resonant converter, the peak drain current at the same output load condition becomes different in various ac input voltages (85 vac to 265 vac), that is, when the ac input volt- age is high, the peak drain current is low because the operation frequency becomes high. when the ocp threshold voltage is fixed constant, the output cur- rent, i out , in an ocp operation increases according to an increase of ac input voltage, as shown in (a) i out without input compen- sation of figure 46. in the maximum ac input voltage range, in order to control output current at ocp operation, i out(ocp) , an external ocp input compensation circuit (d x1 , d zx1 , r x1 ) is added as shown in figure 47. for more details as to how to set it, refer to the next section, input compensation function for overcurrent protection. surge pulse voltage width at turning on ocp detection period s/gnd t on(leb) v rocp figure 44. minus detection ocp circuit figure 45. ocp pin voltage, converted from mosfet drain current by r ocp figure 46. input compensation ocp circuit: (a) i out without input compensation; (b) i out with appropriate input compensation; (c) with inappropriately set input compensation, more than enough amount of compensation, i out cannot meet target ac input voltage (v) a c b 85 265 output current at ocp, i out(ocp) i out target output level + - 8(1) 1(2) 3(5) v r ocp rocp logic controller chip drive ocp comparator ? 0.6v c5 r3 c3 p c2 d/st s/gnd ocp reg filter lc55xxd (lc55xxf)
33 sanken electric co., ltd. lc5500-an, rev.1.2 r ocp i ocp compensation current, i i d c2 forward voltage e fw1 n p n s n d d5 r1 s/gnd ocp d/st c5 1(2) 3(5) 8(1) r3 d7 c7 d6 c4 r4 d x1 d zx1 r x1 flyback voltage e rev1 lc55xxd (lc55xxf) ps d e in figure 48. ocp input compensation circuit figure 49. ocp input compensation d/st vcc s/gnd r ocp r1 r3 c4 8(1) 2(4) 3(5) 1(2) p c2 c3 c5 lc55xxd (lc55xxf) ocp l2 d5 d6 c7 d7 d x1 d zx1 r x1 r4 d figure 47. input compensation ocp circuit } ac input voltage = 85 v ac input voltage = 265 v time time auxiliary winding forward voltage e fw1 0 0 d zx1 ocp input compensation starting point: e fw1 d zx1 e fw2 input compensation function for overcurrent protection the auxiliary winding forward voltage e fw1 is proportional to the input voltage, e in . e fw1 is applied to d zx1 , and r x1 and r3 translate the voltage e fw1 ? zener voltage of d zx1 , into the input compensation current, i. this input compensation current, i, creates the voltage of r 3 i, and it lowers the compensated ocp threshold voltage to less than the original ocp threshold voltage, v ocp = ?0.6 v. this way, when e in is high, the compensation amount becomes high. the d zx1 zener diode is used to set the voltage at which the input compensation begins, so choose the zener voltage value that is equal to e fw1 at the time when input compensation begins. optimize the circuit in a way to minimize the difference between the overcurrent points at low and high ac input voltage. also ensure that the output current meets its target over the entire ac input voltage range, as the normal curve shown in figure 46. the ocp pin voltage, including surge voltage, must not exceed its absolute maximum rating of ?2.0 to 5.0 v at the highest ac input voltage. ocp threshold voltage with and without the ocp input compensation circuit without the input compensation circuit, as shown in the figure 50 upper panel, the overcurrent detecting voltage is equal to the sum of the overcurrent protection threshold voltage, v ocp = ? 0.60 v, and the voltage across r3 from the ocp pin source current, i ocp = ? 40 a. =? v rocp |r ocp i dp | = ? |v ocp | + r 3 |i ocp | (6) in the converse situation, with the input compensation circuit, as shown in the figure 50 lower panel, the overcurrent detecting voltage is equal to the sum of the overcurrent protection thresh- old voltage, v ocp = ? 0.60 v, the voltage across r3 from the ocp pin source current, i ocp , and the voltage across r3 from the input compensation current, i : = ? v ' rocp |v ocp | + r 3 | i ocp | ? r 3 i a ? ? a ? ? (7) ? determining ocp pin input compensation circuit component values given: e in(pk) = c2 voltage i dp = mosfet peak drain current v fx1 = d x1 forward voltage d zx1 = d zx1 zener voltage
34 sanken electric co., ltd. lc5500-an, rev.1.2 1. the overcurrent detecting peak drain current, i dp(ocp) , without the input compensation circuit, is expressed by the following, based on equation 6, from figure 50, upper panel: = i dp(ocp) r ocp | v ocp | + r 3 | i ocp | (8) 2. on the other hand, the overcurrent detecting peak drain current, i' dp(ocp) , with the input compensation circuit, is expressed by the following, based on equation 7, from fig- ure 50, lower panel: = i ' dp(ocp) r ocp | v ocp | + r 3 (| i ocp | ? i ) (9) here, i' dp is the peak drain current where the output power of the maximum ac input voltage becomes the same as that limited by ocp at the minimum ac input voltage. 3. from equations 8 and 9, the compensation current, i, of the input compensation circuit, is expressed as follows: ( | i dp(ocp) | ? | i ' dp(ocp) | ) i = r ocp r 3 (10) 4. the forward voltage, e fw1 , at c2 peak voltage e in(pk) (max) is expressed as follows: n p n d e in(pk) (max) = e fw1 (11) 5. next, r x1 is expressed by the following, in order to let the compensation current, i, flow at the maximum ac input volt- age, e in(pk) (max): e fw1 ? d zx1 ? v fx1 r x1 + r 3 + r ocp = i (12) assuming: r3, r ocp << r x1 i e fw1 ? d zx1 ? v fx1 = r x1 (13) from equations 11 and 13: ? i ( d zx1 + v fx1 ) = n p r x1 n d e in(pk) (max) (14) ? ac input compensation circuit design example with universal input here is an example of design specification and calculation: given: ac input voltage: 85 to 265 vac output power: 40 w transformer primary winding: 40 t transformer auxiliary winding: 6 t r ocp = 0.2 r 3 = 220 d x1 forward voltage: 0.8 v tentatively, ocp input compensation start voltage is set to the voltage of 100 to 130 vac. at this time, ocp input compensation starting voltage is set to 120 vac. figure 50. compensated drain current waveforms r3 r3 r3 r ocp i dp r3 i dp increase decrease r ocp i ocp i ocp i i ocp i i ocp i dp i d i d i dp r3 r3 r ocp r3 v ocp v ocp r3 r ocp i dp ' i dp ' i dp ' i dp ' s/gnd ocp r ocp r3 r x1 r ocp r ocp r ocp r3 s/gnd s/gnd ocp 1(2) 1(2) with input compensation circuit without input compensation circuit v ocp 3(5) 3(5) v ocp v ocp v ocp i ocp i ocp i s/gnd
35 sanken electric co., ltd. lc5500-an, rev.1.2 1. calculate e fw1 at 120 vac input: = e fw1 n p n d = e in(pk) (max) n p n d v in(ocp_st) 2 == 40 6 120 2 25.5 (v) (15) thus, select 27 v as the zener value for dz x1 . assuming: i dp(ocp) at the minimum ac input voltage = 3.0 a i' dp(ocp) at the maximum ac input voltage (when the output power of the maximum ac input voltage becomes the same as that limited by ocp at the minimum ac input voltage) = 1.9 a 2. the compensation current, i, is calculated using equation 10: = i 0.2 ( ) 220 ( ) = 1 (ma) (3.0 (a) ? 1.9 (a)) 3. r x1 can be calculated using equation 14: = = r x1 40 (t) 1 (ma) 28.4 (k ) 6 (t) 265 (vac) 2 ? (27 (v) + 0.8 (v)) thus, select r x1 = 27 k out of the e12 series. finally, ensure that these values work to achieve the output power cited as (b), i out with appropriate input compensation, of gure 46, by the actual operation, and adjust them if necessary. thermal shutdown protection thermal shutdown protection is activated when the temperature of the control circuit in the ic reaches t j(tsd) = 135c(min), and then the ic stops switching operation in latch mode. maximum on-width limiting function the maximum on-width, set at t on(max) = 40 s (figure 51), lim- its lower side operation frequency, and it minimizes audible noise from the transformer, as well as power stress on the incorporated mosfet and secondary rectifier at low ac input or during tran- sient periods such as at switching ac mains on or off. ensure that the actual on-width at the minimum ac input and the maximum load condition does not reach t on(max) = 40 s. if that does happen, redesign the transformer, such as by reducing the primary inductance or reducing the duty cycle by lowering the turns ratio of n p / n s . design considerations peripheral components take care to use properly rated and proper type of components. ? output smoothing capacitor. consider design margins for rat- ings of ripple current, voltage, and temperature in selecting the output capacitor. a low impedance capacitor, designed to be tolerant against high ripple current, is recommended. ? transformer. consider design margins for temperature rise, resulting from copper losses and core losses, in designing or selecting a transformer. switching current contains a high frequency component that causes the skin effect; therefore, consider a current density of 3 to 4 a/mm 2 and select a wire gauge based on rms current. in the event further temperature measurement is necessary and it is necessary to increase surface area of the wire, try the fol- lowing measures: ? increase the quantity of parallel wires ? use litz wire ? increase the diameter of the wires ? current detection resistor, r ocp . choose a low equivalent series inductance and high surge tolerant type for the current detection resistor. if a high inductance type is used, it may cause malfunctioning because of the high frequency current running through it. transformer design the transformer design is the same as for an rcc (ringing choke converter, or self-oscillation flyback converter) transformer design. however, a quasi-resonant operation includes a certain delay to turn-on, so duty cycle must be compensated. i d v ds time time maximum on-time figure 51. maximum on-width
36 sanken electric co., ltd. lc5500-an, rev.1.2 determine the minimum operation frequency, f 0 , and the flyback voltage, e f , and then calculate the primary inductance, l p , as follows: = l' p 2 p o f s (min) h ( v inrms(min) d on ) 2 + v inrms(min) d on f s (min) c v ? ? ? ? ? ? ? ? 2 (16) where v inrms(min) is the effective value (rms) of the sine wave of the minimum ac input voltage, p o is the maximum output power: p o = v o i o (17) where v o is the output voltage, and i o is the maximum output current, f s(min) is the operation frequency at the peak voltage of the sine wave of ac input voltage (the minimum operation frequency), is the efficiency rate: 80% to 90%, c v is the voltage resonant capacitor (c3) rating: 47 to 470 pf, for general application d on is the maximum duty cycle, not compensated for the quasi- resonant delay time, at the minimum ac input voltage: = d on e f 2 v inrms(min) + e f (18) e f is the flyback voltage: e f = ( n p / n s ) ( e o + v f ) (19) where n p is the number of turns of the primary winding, n s is the number of turns of the secondary winding, and v f is the forward voltage of the secondary rectifier, d8, approximately 0.7 v e f is determined by the power mosfet breakdown voltage and the surge voltage. because the breakdown voltage of the power mosfet of this ic is 650 v, when it is used with the specified universal input range, the target voltage of e f is 100 to 150 v. quasi-resonant delay time, t ondly : = t ondly l ' p c v (20) maximum duty cycle, compensated for quasi-resonant delay time (t ondly ), d' on : d ' on = (1 ? f s(min) t ondly ) d on (21) input rms current of the sine wave of the minimum ac input voltage, i inrms(max) : = i inrms (max) v inrms(max) p o (22) peak drain current, compensated for quasi-resonant delay time (t ondly ), i dp(dly) : = i dp(dly) d ' on v in(rms(min) 2 2 p o (23) in transformer design, al-value and n p must be set in a way that the ferrite core does not saturate. here, use ampere turn value (at), the result of i dp(dly) n p and the graph of ni-limit (at) versus al-value (figure 52 is an example of it). ni-limit is the limit that the ampere turn value should not exceed; otherwise the core saturates. so use the graph and equation 24, which expresses the relationship of l p , al-value, and n p to appropriately set these values. in addition, target 30% below the ni-limit curve as a design margin in consideration of temperature effects and other variations, as expressed by the formulas below: ni-limit n p i dp(dly) 130% (24) = n p l p al value (25) then, the rest of the winding turns are determined by the formu- las below. = n s e f v o + v f n p (26) = n d v cc v o + v f n s (27) figure 52. example of ni-limit versus al-value characteristics ni-limit(at) al-value(nh/t 2 ) saturation region boundary margin=30% design point (example)
37 sanken electric co., ltd. lc5500-an, rev.1.2 trace and component layout design pcb circuit trace design and component layout affect ic func- tioning during operation. unless they are proper, malfunction, significant noise, and large power dissipation may occur. circuit loop traces flowing high frequency current, as shown in figure 53, should be designed as wide and short as possible to reduce trace impedance. in addition, earth ground traces affect radiation noise, and thus should be designed as wide and short as possible. switching mode power supplies consist of current traces with high frequency and high voltage, and thus trace design and component layout should be done in compliance with all safety guidelines. furthermore, because an integrated power mosfet is being used as the switching device, take account of the positive thermal coefficient of r ds(on) for thermal design. figures 54, 55, and 56 show practical trace design examples and considerations for the lc551xd, lc552xd and lc552xf series respectively. in addition, observe the following: ? traces among the s/gnd pin, r ocp , c2, t1(primary winding), and d/st pin: the traces carry the switching current; therefore, widen and shorten them as much as possible. if the ic and the electrolytic capacitor c2 are apart, place a film capacitor (0.1 f with appropriate voltage rating) close to the ic or the transformer in order to reduce series inductances of the traces against high frequency current. figure 54. lc551xd (non-isolated designs) peripheral circuit connection example main circuit gnd circuit of control circuit secondary rectification circuit d c4 c10 zd1 r ocp d6 c5 d8 d5 d9 c3 d7 c6 r1 t1 r3 r4 c7 u1 lc551xd d/st 8 1 65 4 3 2 v cc s/gnd ocp comp isense nf c2 c8 r5 clamping snubber a p s figure 53. high frequency current loops
38 sanken electric co., ltd. lc5500-an, rev.1.2 ? traces among the s/gnd pin, c4(?), t1(auxiliary winding d), r1, d5, c4(+), and vcc pin: this trace is for supplying voltage to ic. widen and shorten the traces as much as possible. if the ic and the electrolytic capacitor c4 are apart, place a film or ceramic capacitor (0.1 to 1.0 f) as close to vcc pin and the s/gnd pin as pos- sible. ? current detection resistor r ocp : place r ocp as close to the s/gnd pin as possible. in addition, in order to avoid interference of the switching current with the control circuit, connect the ground of the control circuit to the s/gnd pin as close as possible. connect r3 as close to r ocp as possible (at the point a of figures 54, 55, and 56) with dedicated traces. ? secondary side, traces among t1(secondary winding s), d8, and c10: the secondary-side switching current runs through this trace. widen and shorten the traces as much as possible. thin and long traces cause the series inductance to be high and it results in high surge voltage on the power mosfet when it turns off. therefore, proper layout pattern design helps to increase voltage margin of the power mosfet to its break- down voltage and reduce power stress and loss of the clamping snubber circuit. figure 55. lc552xd (isolated designs) peripheral circuit connection example main circuit control circuit gnd circuit secondary rectification circuit u1 con- troller chip s d p c4 s/gnd ocp fb nf 4 5 2 8 pc1 d6 a c5 d8 c10 t1 d5 c3 c2 d7 vcc d/st r1 r3 r4 r7 c7 c17 clamping snubber lc552xd 3 1 c6 r ocp
39 sanken electric co., ltd. lc5500-an, rev.1.2 figure 56. lc552xf (isolated designs) peripheral circuit connection example main circuit control circuit gnd circuit secondary rectification circuit clamping snubber u1 con- troller chip s d p c4 s/gnd ocp fb pc1 d6 a c5 d8 c10 t1 d5 c3 c2 d7 vcc d/st r1 2 1 4 6 r3 r4 r7 c6 c7 5 c17 lc552xf r ocp
40 sanken electric co., ltd. lc5500-an, rev.1.2 ? the contents in this document are subject to changes, for improvement and other purposes, without notice. make sure that this is the latest revision of the document before use. ? application and operation examples described in this document are quoted for the sole purpose of reference for the use of the products herein and sanken can assume no responsibility for any infringement of industrial property rights, intellectual property rights or any other rights of sanke n or any third party which may result from its use. ? although sanken undertakes to enhance the quality and reliability of its products, the occurrence of failure and defect of se miconductor products at a certain rate is inevitable. users of sanken products are requested to take, at their own risk, preventative measures including safety design of the equipment or systems against any possible injury, death, fires or damages to the society due to device failure or malfunction. ? sanken products listed in this document are designed and intended for the use as components in general purpose electronic equ ipment or apparatus (home appliances, office equipment, telecommunication equipment, measuring equipment, etc.). when considering the use of sanken products in the applications where higher reliability is required (transportation equipment and its control systems, traffic signal control systems or equipment, fire/crime alarm systems, various safety devices, etc.), and whenever long life expectancy is required even in general purpose electronic equipment or apparatus, please contact your nearest sanken sales representative to discuss, prior to the use of the products herein. the use of sanken products without the written consent of sanken in the applications where extremely high reliability is requir ed (aerospace equipment, nuclear power control systems, life support systems, etc.) is strictly prohibited. ? in the case that you use our semiconductor devices or design your products by using our semiconductor devices, the reliabilit y largely depends on the degree of derating to be made to the rated values. derating may be interpreted as a case that an operation range is set by derating the l oad from each rated value or surge voltage or noise is considered for derating in order to assure or improve the reliability. in general, derating factors include electric stresses such as electric voltage, electric current, electric power etc., environmental stresses such as ambient temperature, humidity etc. and thermal stress cau sed due to self-heating of semiconductor devices. for these stresses, instantaneous values, maximum values and minimum values must be taken into consideration. in addition, it should be noted that since power devices or ic?s including power devices have large self-heating value, the deg ree of derating of junction temperature (tj) affects the reliability significantly. ? when using the products specified herein by either (i) combining other products or materials therewith or (ii) physically, ch emically or otherwise processing or treating the products, please duly consider all possible risks that may result from all such uses in advance and proceed therew ith at your own responsibility. ? anti radioactive ray design is not considered for the products listed herein. ? sanken assumes no responsibility for any troubles, such as dropping products caused during transportation out of sanken?s di stribution network. ? the contents in this document must not be transcribed or copied without sanken?s written consent.

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